1. Field of the Invention
This invention relates to a method for forming a conductive layer on a semiconductor wafer. More particularly, the present invention relates to a method of forming a conductive layer on a semiconductor wafer of line width smaller than 0.18 microns.
2. Description of the Prior Art
In manufacturing semiconductor devices, the line width is getting smaller, thus the copper metallization will replace the aluminum to meet the RC delay requirement when a process of 0.18 micron or below is followed. Combining TaN and Cu for barrier layer and seed layer with the electroplating deposition is the main trend for the generation of a 0.18-micron process. However, the conformity of the barrier layer and the seed layer is a main issue in fabricating the semiconductor device especially when the process of 0.18 micron or below is utilized.
In some applications, the CVD (Chemical Vapor Deposition) Cu is utilized to fabricate the conductive layer in a semiconductor device to obtain the conformal step coverage, particularly when the line width is small. In general, the copper layer fabricated by CVD uses SF3 containing chemistry as a source, so the resistivity of the resulting copper layer is high. Especially when the thickness of the copper layer is decreased, the resistivity of the copper layer will be increased. Furthermore, the residue after the CVD can create the problem of adhesion between the copper layer and the underlying layer, and the CVD technique is expensive. So the CVD technique suffers from the problems mentioned above, and the CVD technique is suitable for the seed layer of electrochemical deposition when utilizing Cu metallization in 0.18-micron or below process.
To overcome the adhesion problem and to avoid the increase of the resistivity of the Cu layer formed by CVD, the PVD (Physical Vapor Deposition) technique is used in Cu metallization. As shown in FIG. 1, a semiconductor wafer includes a contact hole 10 in the dielectric layer 11 on the substrate 12, and the PVC technique is used to form a barrier layer 15 on the topography of the semiconductor wafer. Generally, the barrier layer 15 is formed of Ta, TiN or TaN. Because the nature of the PVC technique, the overhang 19 is formed in the barrier layer 15 at the corner 17 of the dielectric layer 11.
Before filling the contact hole 10 with copper, a seed layer 20 composed of copper as shown in FIG. 2 is formed on the barrier layer 15. When the seed layer is formed by the PVD technique, the overhang 21 of the seed layer 20 is also formed on the overhang 19 of the barrier layer 15. Even though the seed layer 20 is formed by a ECD (Electrochemical Deposition) technique. Because the current density on the surface of the overhang 19 is greater than the other portion of the barrier layer 15, the deposition rate of copper at the overhang 19 is higher than the other portion of the barrier layer 15. Accordingly, the overhang 21 of the seed layer 20 is formed at the overhang 19, and the conformity of the seed layer 20 is poor even though the electrochemical deposition is utilized.
Because of the overhang formed by the PVD technique, it is very difficult to fill copper in the contact hole. This is particularly true when the 0.18-micron process or below is utilized, in which case the opening of the contact hole may be closed, and the failure of the formation of a via plug may result. A cheap technique that can fabricate a conformal seed layer without the issue of adhesion is necessary in the process of 0.18-micron or below.
In the other respect, the chemical mechanical polish (CMP) is often used to polish the surface of the semiconductor wafer to reduce the altitude difference of the surface of the semiconductor. Yet the higher surface and the lower surface are simultaneously polished during the CMP process. So the resulting planarity is not good enough, thus the planarity of the semiconductor wafer can be further improved by another method.